Session: 2026-08-20 — Building toward "write a kernel driver that enables SVM and does a VMRUN/VMEXIT round-trip"
A core is one independent processing unit inside your CPU chip. Your Ryzen 9 9900X has 12 cores — 12 separate copies of the Zen 5 microarchitecture on one chip. Each core can fetch, decode, and execute ISA instructions independently and simultaneously.
For a hypervisor: each core has its own SVM hardware that must be enabled individually. 12 cores = 12 separate "flip the switch" setup routines.
Follow-up: CPU parallelism vs GPU parallelism
CPUs do have parallelism — 12 cores = 12 things truly simultaneous. GPUs have massive parallelism — ~10,752 tiny cores doing the same simple op on different data. CPU cores are few and powerful (complex branching); GPU cores are many and simple (bulk arithmetic). Hypervisors need CPU-style parallelism. Neural net training needs GPU-style.
Follow-up: Threads, Concurrency, Parallelism
Thread = one sequential instruction stream. Concurrency = multiple threads making progress, possibly by one core time-slicing between them. Parallelism = multiple threads running at the literal same instant on different cores. Multi-threaded program on 1 core = concurrency; on multiple cores = parallelism.
A kernel driver is a program that runs at Ring 0, the same privilege level as the Windows kernel itself. Normal programs (Chrome, VS Code) run at Ring 3 and are blocked from directly accessing hardware. A kernel driver runs inside the kernel, so it can access hardware — including the SVM registers on each core.
Why you need one: SVM can only be enabled by code running at Ring 0 (kernel privilege). A normal .exe at Ring 3 can't do it. So you write a kernel driver, load it into Windows, and from Ring 0 it flips the SVM switch on each core. The driver is your launchpad — once SVM is on, you're at Ring -1 and the hypervisor is running.
Follow-up: MSRs, RDMSR/WRMSR, and EFER.SVME
MSRs (Model-Specific Registers) = special config registers on each core (separate from general-purpose registers like RAX/RBX). Accessed with Ring 0-only instructions: RDMSR (read) and WRMSR (write). EFER = one specific MSR; its bit 12 (SVME) is the SVM on/off switch for that core. Each core has its own EFER, so you WRMSR 12 times — once per core.
Follow-up: Ring numbering explained
x86 has real Rings 0–3 (lower = more privilege). Rings 1 & 2 are unused on modern systems. "Ring -1" (hypervisor/SVM) and "Ring -2" (SMM/firmware) are informal names — the community extended the convention below 0 for things more privileged than the kernel.
SVM (Secure Virtual Machine) is AMD's hardware virtualization technology — circuits baked into each core that give it the ability to split into two modes: host mode (where your hypervisor runs) and guest mode (where the OS and its programs run, thinking they have full control).
Before SVM is enabled, a core is just running code normally — no concept of host or guest. After you set EFER.SVME = 1, the core gains new capabilities: it can now execute VMRUN to enter guest mode and automatically trap back to host mode on a VMEXIT. The hypervisor runs in host mode and controls what the guest is allowed to do.
The key data structure is the VMCB (Virtual Machine Control Block) — a block of memory that describes the guest's entire state: its registers, what events to intercept, and its memory configuration. When you execute VMRUN, you hand the CPU a pointer to a VMCB, and the core loads the guest state from it and starts executing as the guest.
Unlocks after SVM is confirmed.